1. Field of the Invention
The present invention relates to a multi-thread processor and its hardware thread scheduling method, and in particular to a multi-thread processor having a thread scheduler that schedules the execution order of a plurality of hardware threads and its hardware thread scheduling method.
2. Description of Related Art
In recent years, multi-thread processors have been proposed in order to improve the processing power of processors. A multi-thread processor has a plurality of threads each of which generates an independent instruction flow. Further, the multi-thread processor performs arithmetic processing while changing the instruction flow to be processed in the arithmetic circuit that processes instructions in pipeline processing between a plurality of instruction flows that are generated by the respective plurality of threads. At this point, the multi-thread processor can execute an instruction generated by one thread in one execution stage of the pipeline while executing an instruction generated by another thread in another execution stage. That is, in the arithmetic circuit of the multi-thread processor, instructions that are independent of each other are executed in different execution stages from each other. In this way, the multi-thread processor can process each instruction flow smoothly while reducing the time period during which no instruction is processed in an execution stage of the pipeline, and thus improving the processing power of the processor.
Japanese unexamined Patent Application Publication No. 2007-317171 discloses an example of such a multi-thread processor. The multi-thread processor described in Japanese unexamined Patent Application Publication No. 2007-317171 includes a plurality of processor elements and a parallel processor control unit that switches the thread of each processor element. Further, the parallel processor control unit counts the execution time of the thread being executed in the processor element, and when the counted time has reached the allocated time for the thread, outputs a time-out signal and switches the thread to be executed by the processor element based on the time-out signal and execution order information retained in an execution order register.
As described above, the instruction flow to be processed in the arithmetic circuit is switched between instruction flows generated by the respective threads in accordance with a schedule in the multi-thread processor. Japanese unexamined Patent Application Publication No. 2008-52750 discloses an example of such a thread scheduling method. In the multi-thread processor described in Japanese unexamined Patent Application Publication No. 2008-52750, a plurality of threads are executed in a circular manner, and each thread is executed for its allocated time in each round. That is, in Japanese unexamined Patent Application Publication No. 2008-52750, a schedule that is established in a fixed manner is executed in a circular manner, so that each thread is executed with a predefined execution time ratio.
Further, Japanese unexamined Patent Application Publication No. 2006-155480 discloses another thread scheduling method. Specifically, Japanese unexamined Patent Application Publication No. 2006-155480 discloses a round-robin method and a priority method as a thread scheduling method. In the round-robin method, threads that are put in a queue are selected and executed one by one at regular intervals. Therefore, in the round-robin method, threads in the queue are impartially assigned to and executed in the CPU at regular intervals. Further, in the priority method, threads are executed in order of their priorities. More specifically, in the priority method, a queue is established for each priority and each thread is put in one of the queues according to its priority. Then, threads are selected, and assigned to and executed in the CPU in descending order of the priority.